FIG. 1 shows an embodiment of a known pulse width modulated single-ended forward DC/DC converter with self-driven synchronized rectifiers V1, V2, illustrated as field effect transistors (FETs), connected across a secondary winding N2 of a transformer TR in the converter.
An output filter comprising an inductor L and a capacitor C is connected across V2 to provide an output voltage U2 across the capacitor C in a manner known per se.
A primary winding N1 of the transformer TR is connected with one of its terminals to a (+) terminal 1 of a source of varying input DC voltage U1, and with its other terminal to the drain of a primary switch in the form of a FET V3. The source of V3 is connected to a (−) terminal 2 of the voltage source U1. The gate of V3 is pulse width modulated such that its duty cycle is varied in response to the varying input voltage U1 to keep the output voltage U2 at a desired value. To accomplish this, the actual value of the output voltage U2 is sensed by a voltage regulator 3 and compared to the desired value of the output voltage, that is set in the voltage regulator 3. In response to differences between the actual value and the desired value, the voltage regulator 3 outputs a control signal to a control circuit 4. In response to the control signal, the control circuit 4 in its turn outputs a pulse width modulated control signal to the gate of V3 to vary the duty cycle of V3 such that the actual value of U2 equals the desired value. During the off period of the primary switch V3, the core of the transformer TR has to be reset to discharge the leakage inductance of the transformer TR.
To reset or demagnetize the transformer TR, a so-called snubber circuit is provided in a manner known per se to absorb energy during the off period of V3. The snubber circuit comprises a series circuit of a diode D1 and a capacitor C1 that is connected in parallel with the primary winding N1 and a resistor R1 which is connected to the terminals of the capacitor C1. When V3 is turned off, energy which has been accumulated in the primary winding N1 of the transformer TR is transferred to the capacitor C1 and dissipated by the resistor R1.
The FETs V1 and V2 are both controlled by the transformer TR in such a manner that V1 is on when V3 is on, while V2 is on when V3 is off. Thus, V2 is on when the transformer TR is being reset. At higher input voltages U1, the on periods of V3 will be shorter. Hereby, the transformer TR will be reset more quickly. This will result in a longer so-called dead time, i.e. the time when there is no voltage across the transformer TR. As a consequence, V2 will not have any gate drive during such times. Instead, its body diode that generates more losses, will conduct. Hereby, the efficiency of the converter will be lower. Also, the presence of dead time means that the primary switch V3 is exposed to higher voltage than necessary.
FIG. 2 is a diagram illustrating the voltage UN1 across the primary winding N1 of the transformer TR versus the time t. The primary switch V3 is turned off at time t1 and is turned on again at time t3. The transformer TR is supposed to have been demagnetized at time t2. Thus, the dead time lasts from time t2 to time t3 in FIG. 2. The dead time depends on the on-time of V3 such that a shorter on-time gives a longer dead time.
To improve the efficiency that is associated with good timing of the secondary switches, it is possible to control the gate drive of V2 from the primary side of the transformer TR. The disadvantages of such a solution are increased complexity and increased costs.